module div2(clk_50,clr,z);

input clk_50,clr;
output z;

parameter DELAY=0;
reg [DELAY:0]Q = 0;
assign z=Q[DELAY];

always@(posedge clk_50 or negedge clr) begin
    if(clr==0)Q<=16'h00;
    else Q<=Q+1;
end

endmodule 
